An analog-to digital converter (ADC) converts an analog input voltage to a digital representation. Many ADC converts operate according to a successive approximation register (SAR) technique. SAR ADCs sequentially compare the analog input voltage to various reference voltage levels which are generated by a digital-to-analog converter (DAC). During a first clock cycle, the sampled input voltage is compared to half of the reference voltage output by the DAC. If the analog input voltage is greater than half the reference voltage, then a respective bit decision relating to the most significant bit (MSB) is made. During the next clock cycle, the input voltage is compared to three quarters or one quarter of the reference voltage in accordance with the preceding MSB decision, and a further bit decision is made relating to the next less significant bit (MSB−1). The conversion procedure carries on accordingly, and the DAC output voltage converges successively to the analog input voltage, while evaluating one bit during each clock cycle.
Some SAR ADCs implement a charge redistribution technique which uses an array of capacitors. The charge stored on the capacitors is manipulated to perform the conversion from analog to digital. Some SAR ADCs also include a least significant bit (LSB) capacitor that is connected to a resistor network. Various tap points along the resistor network are coupled to the LSB capacitor to generate additional bit decisions.
Because SAR ADCs typically include capacitors and resistors, the voltages generated based on the reference voltage take a finite amount of time to settle before the comparison to make a bit decision can be made. The settling time of the ADC thus is a significant parameter that can detrimentally effect ADC performance.